ISOOC proposes an open standard for Port 80 debug information to enable ubiquitous on-site troubleshooting, simplifying PC building and reducing return rates.
Summary
In the past, generic Port 80 debug information was available via LPC bus access on every motherboard and could be enabled with third-party debug tools. However, due to the technology change this is no longer possible. Furthermore, few if any motherboards below USD $300 that provide detailed on-board Port 80 system debug information. As a result, if the system does not boot, in most cases the end-user cannot try to diagnose the system.
ISOOC proposes to develop an open standard for accessing POST information for debug purposes with representatives from the relevant stakeholders in the industry. The open standard should enable third-parties to enable POST information on any PC system.
Identified Problem
Today, there are few if any motherboards below USD $300 that provide detailed on-board Port 80 system debug information. As a result, if the system does not boot, in most cases the end-user cannot try to diagnose the system. Thus, they must return the product to the store and go through the RMA process.
In the past, generic Port 80 debug information was available via LPC bus access on every motherboard and could be enabled with third-party debug tools. However, due to the technology change this is no longer possible:
- PCI to PCIe transition resulted in the loss of LPC bus access except via the TPM header
- Hardware TPM is often replaced by software TPM, so no physical header present
- Modern eSPI bus which provides Port 80 debug information typically does not have a header on the motherboard.
Furthermore, motherboard vendors use proprietary methods to enable debug information.
- UEFI port 80 redirection to PCI-e to PCI bridge chip (GIGABYTE; disabled on production BIOSes)
- Serial output through SIO function (ASUS & MSI; different headers and data format)
Proposed Solution
Descriptive
Develop an open standard for accessing POST information for debug purposes with representatives from the relevant stakeholders in the industry. The open standard should enable third-parties to enable POST information on any PC system.
The standard should include specifications of a debug header including mechanical, electrical characteristics, and data format to adhere to. The header should be usable in a range of form factors and attempt to minimize the amount of space taken up on the product it’s implemented on.
Technical
Most existing proprietary solutions output port 80 data over universal asynchronous receiver-transmitter (UART) through a specific header on their product. The data is often sent by the “Super I/O”-chip or the embedded controller.
It’s proposed to use the seemingly most common UART format of 9600 baud, eight data bits, zero parity bits, one stop bit, and no hardware flow control. Many existing solutions also currently use standard 2.54mm rectangular pin headers with different pinouts.
It’s suggested to use a smaller sized header to allow for easier placement on motherboards with restricted space and to use a widely available connector type available from multiple sources. Additionally, it would be beneficial if the header is polarized to prevent wrongful insertion by the user.
Visual
To be added.
Proposed Standard
To be added
Timeline, Milestones, and Next Steps
- 2Q 2023:
- Formalize the technical standard proposal
- Evaluate proposal with key industry stakeholders
- Q1 2023:
- January 2, 2023: publish workgroup proposal draft v0.1